119 lines
3.6 KiB
Rust
119 lines
3.6 KiB
Rust
// Copyright 2020-2022 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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use tock_registers::register_bitfields;
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register_bitfields! [u32,
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// Generic or shared bitfields
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pub Task [
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ENABLE OFFSET(0) NUMBITS(1)
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],
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pub Byte [
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VALUE OFFSET(0) NUMBITS(8)
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],
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pub Busy [
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/// Asserted when AES_BUSY or DES_BUSY or HASH_BUSY are asserted or when the DIN FIFO is not empty
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BUSY OFFSET(0) NUMBITS(1) [
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Ready = 0,
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Busy = 1
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]
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],
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// CC_CTL register bitfields
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pub CryptoMode [
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/// Determines the active cryptographic engine
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MODE OFFSET(0) NUMBITS(5) [
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Bypass = 0,
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Aes = 1,
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AesToHash = 2,
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AesAndHash = 3,
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Des = 4,
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DesToHash = 5,
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DesAndHash = 6,
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Hash = 7,
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AesMacAndBypass = 9,
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AesToHashAndDout = 10
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]
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],
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// HOST_RGF register bitfields
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pub Interrupts [
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/// This interrupt is asserted when all data was delivered to DIN buffer from SRAM
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SRAM_TO_DIN OFFSET(4) NUMBITS(1),
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/// This interrupt is asserted when all data was delivered to SRAM buffer from DOUT
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DOUT_TO_SRAM OFFSET(5) NUMBITS(1),
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/// This interrupt is asserted when all data was delivered to DIN buffer from memory
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MEM_TO_DIN OFFSET(6) NUMBITS(1),
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/// This interrupt is asserted when all data was delivered to memory buffer from DOUT
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DOUT_TO_MEM OFFSET(7) NUMBITS(1),
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AXI_ERROR OFFSET(8) NUMBITS(1),
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/// The PKA end of operation interrupt status
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PKA_EXP OFFSET(9) NUMBITS(1),
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/// The RNG interrupt status
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RNG OFFSET(10) NUMBITS(1),
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/// The GPR interrupt status
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SYM_DMA_COMPLETED OFFSET(11) NUMBITS(1)
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],
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pub RgfEndianness [
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/// DOUT write endianness
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DOUT_WR_BG OFFSET(3) NUMBITS(1) [
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LittleEndian = 0,
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BigEndian = 1
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],
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/// DIN write endianness
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DIN_RD_BG OFFSET(7) NUMBITS(1) [
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LittleEndian = 0,
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BigEndian = 1
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],
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/// DOUT write word endianness
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DOUT_WR_WBG OFFSET(11) NUMBITS(1) [
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LittleEndian = 0,
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BigEndian = 1
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],
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/// DIN write word endianness
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DIN_RD_WBG OFFSET(15) NUMBITS(1) [
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LittleEndian = 0,
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BigEndian = 1
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]
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],
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// DIN and DOUT register bitfields
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pub LliWord1 [
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/// Total number of bytes to read using DMA in this entry
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BYTES_NUM OFFSET(0) NUMBITS(30),
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/// Indicates the first LLI entry
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FIRST OFFSET(30) NUMBITS(1),
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/// Indicates the last LLI entry
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LAST OFFSET(31) NUMBITS(1)
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],
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pub HashControl [
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// bit 2 is reserved but to simplify the logic we include it in the bitfield.
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MODE OFFSET(0) NUMBITS(4) [
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MD5 = 0,
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SHA1 = 1,
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SHA256 = 2,
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SHA224 = 10
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]
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],
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pub PaddingConfig [
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/// Enable Padding generation. must be reset upon completion of padding.
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DO_PAD OFFSET(2) NUMBITS(1)
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]
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];
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